Matched integrated electronic components

ABSTRACT

A switchable integrated electronic device includes at least three elements r 1  . . . r 14 , s 1  . . . s 14  series coupled in a chain between a first port and a second port and includes a node between successive elements r 1  . . . r 14 , s 1  . . . s 14  of the chain. There is a switch means for coupling a selectable one of the nodes to a third port. If successive elements r 1  . . . r 14 , s 1  . . . s 14  in the chain are denoted r i , i=1 to N, and if adjacent positions occupied by the elements are numbered consecutively 1 to N, then element r i  occupies position 
     
       
         
           
             
               
                 ⌊ 
                 
                   
                     N 
                     + 
                     1 
                   
                   2 
                 
                 ⌋ 
               
               + 
               
                 
                   
                     
                       ( 
                       
                         - 
                         1 
                       
                       ) 
                     
                     i 
                   
                   · 
                   2 
                   · 
                   
                     ⌊ 
                     
                       i 
                       2 
                     
                     ⌋ 
                   
                 
                  
                 
                   
                       
                   
                    
                   
                       
                   
                 
                  
                 for 
                  
                 
                     
                 
                  
                 i 
               
             
             = 
             
               1 
                
               
                   
               
                
               to 
                
               
                   
               
                
               
                 ⌊ 
                 
                   N 
                   2 
                 
                 ⌋ 
               
             
           
         
       
     
     and position 
     
       
         
           
             
               
                 ⌊ 
                 
                   
                     N 
                     + 
                     1 
                   
                   2 
                 
                 ⌋ 
               
               + 
               
                 
                   
                     
                       ( 
                       
                         - 
                         1 
                       
                       ) 
                     
                     i 
                   
                   · 
                   
                     ( 
                     
                       
                         2 
                         · 
                         
                           ⌊ 
                           
                             
                               N 
                               - 
                               i 
                             
                             2 
                           
                           ⌋ 
                         
                       
                       + 
                       1 
                     
                     ) 
                   
                 
                  
                 
                     
                 
                  
                 for 
                  
                 
                     
                 
                  
                 i 
               
             
             = 
             
               
                 ⌊ 
                 
                   N 
                   2 
                 
                 ⌋ 
               
               + 
               
                 1 
                  
                 
                     
                 
                  
                 to 
                  
                 
                     
                 
                  
                 
                   N 
                   .

BACKGROUND

1. Technical Field

The disclosure relates to a switchable integrated electronic device, to electronic circuits incorporating the switchable integrated electronic device, and to a method of manufacturing a switchable integrated electronic device, and in particular the layout of such devices and circuits.

2. Description of the Related Art

The growth of the semiconductor industry is driven by the rapid development and evolution of applications such as wireless communications, imaging processing, internet, and entertainment. In order to reach a high-level of circuit integration and reduce the cost and size, and to enhance competitiveness, analog and mixed-signal circuits are implemented in standard CMOS. Recently, RF and power management functions are increasingly integrated on a digital chip. Device matching is very critical for these circuits, and it is well recognized that the yield and cost can be strongly affected by the design technique adopted, particularly the layout of matching-critical devices. These devices can be transistors, capacitors, inductors or resistors. Matching has become critically important since the process technology is driven by digital circuits where matching is not important.

The matching properties of transistors have been considered by K. Lakshmikumar et al in ‘Characterization and modeling of mismatch in MOS transistors for precision analog design’, IEEE J. Solid-State Circuits, vol. 21, pp. 1057-1066, December 1986 and by M. Pelgromet al in ‘Matching properties of MOS transistors’, IEEE J. Solid-State Circuits, vol. 24, pp. 1433-1440, October 1989, and of transistors and capacitors by J. Shyu et al in ‘Random error effects in matched MOS capacitors and current sources’, IEEE J. Solid-State Circuits, vol. 19, pp. 948-956, December 1984. The matching properties of resistors have been considered by Y. Lin et al in ‘Resistor layout techniques for enhancing yield in ratio-critical monolithic application’, Proc. NWSCAS 2001, vol. 1, pp. 259-261, 2001. Proposed layout techniques, such as common-centroid, deal with matching of two closely placed MOS transistors of equal size only. In practical circuit design, what is frequently required are two devices having large and varying non-unity ratios, which must be precisely matched, which may be referred to as ratio matching. Unfortunately, the layout techniques developed for equal size devices cannot be directly applied to ratio matching.

Resistor layout differs somewhat from that of transistor layout. Straight-line resistors are usually avoided and each resistor is implemented by a series/parallel combination of a number of unit resistors. The most popular layout technique is interleaving. FIG. 1 shows an example of an amplifier where resistors R1 (non-shaded) and R2 (shaded) are implemented each using 9 resistor elements, with R1=R2. The node between R1 and R2 is denoted X. This configuration provides a fixed gain. In many systems a programmable gain amplifier is required and very often the gain must vary over a large range in a certain step size. If the gain is non-unity but fixed, it may still be possible to interleave the resistor elements of R1 and R2 to achieve good matching between R1 and R2. However, device matching becomes more problematic when the resistance ratio is not only large but also varying. For example, automatic gain control for cellular phones generally requires a gain range from −40 dB to +8 dB, in 4 dB steps. In this case, the resistance ratio R2/R1 has to vary from 0.01 to 2.51. As the gain varies, either R1 or R2, or both, must vary. As a result the constellation of R1 and R2, by which we mean the interleaving arrangement of R1 and R2, also varies. If the layout for R1 and R2 is optimized at one gain setting, switching to another gain causes the layout of R1 and R2 to be no longer optimum. This problem is exacerbated if the gain variation and the number of gain steps is large. There exists a need to improve the matching of components with large and varying component ratios.

BRIEF SUMMARY

According to a first aspect of the disclosure there is provided a switchable integrated electronic device, that includes:

at least three elements series coupled in a chain between a first port and a second port with nodes between successive elements of the chain; and

switch means for coupling a selectable one of the nodes to a third port;

wherein, if successive elements in the chain are denoted r_(i), i=1 to N, and if adjacent positions occupied by the elements are numbered consecutively 1 to N, then element r_(i) occupies position

${\left\lfloor \frac{N + 1}{2} \right\rfloor + {{\left( {- 1} \right)^{i} \cdot 2 \cdot \left\lfloor \frac{i}{2} \right\rfloor}{\mspace{11mu} \;}{for}\mspace{14mu} i}} = {1\mspace{14mu} {to}\mspace{14mu} \left\lfloor \frac{N}{2} \right\rfloor}$

and position

${\left\lfloor \frac{N + 1}{2} \right\rfloor + {{\left( {- 1} \right)^{i} \cdot \left( {{2 \cdot \left\lfloor \frac{N - i}{2} \right\rfloor} + 1} \right)}\mspace{14mu} {for}\mspace{14mu} i}} = {\left\lfloor \frac{N}{2} \right\rfloor + {1\mspace{14mu} {to}\mspace{14mu} {N.}}}$

According to a second aspect of the disclosure there is provided a method of manufacturing a switchable integrated electronic device, comprising:

forming at least three elements series coupled in a chain between a first port and a second port and providing nodes between successive elements of the chain; and

forming a switch means for coupling a selectable one of the nodes to a third port;

wherein, if successive elements in the chain are denoted r_(i), i=1 to N, and if adjacent positions occupied by the elements are numbered consecutively 1 to N, then element r_(i) occupies position

${\left\lfloor \frac{N + 1}{2} \right\rfloor + {{\left( {- 1} \right)^{i} \cdot 2 \cdot \left\lfloor \frac{i}{2} \right\rfloor}{\mspace{11mu} \;}{for}\mspace{14mu} i}} = {1\mspace{14mu} {to}\mspace{14mu} \left\lfloor \frac{N}{2} \right\rfloor}$

and position

${\left\lfloor \frac{N + 1}{2} \right\rfloor + {{\left( {- 1} \right)^{i} \cdot \left( {{2 \cdot \left\lfloor \frac{N - i}{2} \right\rfloor} + 1} \right)}\mspace{14mu} {for}\mspace{14mu} i}} = {\left\lfloor \frac{N}{2} \right\rfloor + {1\mspace{14mu} {to}\mspace{14mu} {N.}}}$

Note that in these expressions the symbol └x┘ indicates the largest integer not exceeding the value x, and it is commonly referred to as the floor function. So, for example,

$\left\lfloor \frac{4}{2} \right\rfloor = 2$ and $\left\lfloor \frac{5}{2} \right\rfloor = 2.$

Thus, the disclosure provides a layout for successive series-coupled elements of a switchable electronic device that enables components comprising the elements to be well matched irrespective of the switch setting, by ensuring a good interleaving of the elements of the components. For example, if the elements are resistors that determine the gain of an amplifier, the resistance between the first port and the third port, and between the second port and the third port, can be well matched regardless of gain setting of the amplifier, and hence the ratio of these resistances has a low spread. The disclosure is applicable to components with either large or small ratios.

Optionally the elements all comprise one of a resistive element, a capacitative element, an inductive element, and a semiconductor element. Usually, all of the elements are of the same type, e.g., resistive element, capacitive element, inductive element, semiconductor element etc. Thus the disclosure is applicable to a chain of series coupled resistors, a chain of series coupled capacitors, a chain of series coupled inductors, and a chain of series coupled semiconductor devices etc.

The disclosure also provides an electronic circuit, having a first switchable integrated electronic device according to the first aspect of the disclosure having its first port coupled to a first circuit input and its second port coupled to a circuit output, wherein the elements each comprise a resistive element, and an amplifier having a first amplifier input coupled to the third port of the first switchable integrated electronic device and an amplifier output coupled to the circuit output. In this way, the disclosure provides a switchable-gain amplifier having its gain determined by switchable resistors which are well matched regardless of the selected gain. Hence the gain has a low spread in value.

The disclosure also provides an electronic circuit as stated above and further comprising a second switchable integrated electronic device according to the first aspect of the disclosure having its first port coupled to a second circuit input, its second port coupled to ground or another point in the circuit, and its third port coupled to a second input of the amplifier, wherein the first and second amplifier inputs are respectively inverting and non-inverting, and wherein the elements of the second switchable integrated electronic device each comprise a resistive element. In this way, the disclosure provides a switchable-gain amplifier having inverting and non-inverting inputs and which has its gain determined by switchable resistors which are well matched regardless of the gain setting selected. Optionally, the first and second switchable integrated electronic devices may comprise an equal number of elements and the respective switch means of the first and second switchable integrated electronic devices may be adapted to couple a corresponding selectable one of the nodes of the first and second switchable integrated electronic devices to the respective third ports. This feature enables the inverting and non-inverting inputs to remain well balanced regardless of which gain setting is selected.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The disclosure will now be described, by way of example only, with reference to the accompanying drawings wherein:

FIG. 1 shows a circuit diagram of an amplifier having two resistors and also shows a diagram of the layout of the two resistors;

FIG. 2 is a circuit diagram of a differential amplifier;

FIG. 3 is a circuit diagram showing more detail of the differential amplifier of FIG. 2;

FIG. 4 is a schematic plan layout of resistor elements;

FIG. 5 is a table indicating the resistor elements for different amplifier gain settings;

FIG. 6 is an integrated circuit layout; and

FIG. 7 is a generalized schematic plan layout of resistor elements.

DETAILED DESCRIPTION

Referring to FIG. 2, there is illustrated an audio amplifier 100 capable of driving a load, such as an earphone, in a differential amplifier configuration having inverting and non-inverting inputs, 22 and 24. It includes an operational amplifier 10 having an inverting input 12 and a non-inverting input 14, and an output 16. There is a resistance R1 coupled between a first input 22 of the audio amplifier 100 and the inverting input 12, and a resistance R2 coupled between the inverting input 12 and the output 16. There is a resistance R3 coupled between a second input 24 of the audio amplifier 100 and the non-inverting input 14, and a resistance R4 coupled between the non-inverting input 14 and a ground point GND indicated by reference numeral 18. Instead of being coupled to ground, the resistance R4 may alternatively be coupled to a voltage source or another point in the amplifier 100 circuit.

FIG. 3 illustrates in more detail the audio amplifier 100 of FIG. 2, in particular illustrating how the components R1, R2, R3 and R4 are formed. The combination R1, R2 is formed as a chain of series coupled resistors r₁ . . . r₁₄. There is a switch bank 30 comprising switches a1 . . . a13 for coupling a selectable one of the nodes between any two successive resistors in the chain of resistors r₁ . . . r₁₄ to the inverting input 12. The combination R3, R4 is formed as a chain of series coupled resistors s₁ . . . s₁₄. Correspondingly numbered resistors r₁ . . . r₁₄ and s₁ . . . s₁₄ have nominally equal resistance values, although this is not essential to the disclosure. There is a switch bank 50 comprising switches b1 . . . b13 for coupling a selectable one of the nodes between any two adjacent resistors in the chain of resistors s₁ . . . s₁₄ to the non-inverting input 14. The closure of the switches a1 . . . a13 and b1 . . . b13 is made under the control of a decoder 40, with correspondingly numbered switches a1 . . . a13 and b1 . . . b13 being operated together. In this way, the values of R1 and R2 are selected by partitioning the resistors r₁ . . . r₁₄ by closing a selected one of the switches a1 . . . a13, and the values of R3 and R4 are selected by partitioning the resistors s₁ . . . S₁₄ by closing a selected one of the switches b1 . . . b13. For example, in FIG. 3, switches a11 and b11 are illustrated in the closed position with the other switches all open. In this example R1 includes r₁, r₂ and r₃, R2 includes r₄ . . . r₁₄, R3 includes s₁, s₂, and s₃, and R4 includes s₄ . . . s₁₄. The decoder 40 has thirteen output lines 44 for controlling the thirteen switch pairs a1/b1, a2/b2, . . . a13/b13, and four input lines 42 for a binary signal indicating which of the thirteen switch pairs are to be closed.

If the DC gain of the operational amplifier 10 is large enough, the output voltage Vout of the audio amplifier 100 can be written as:

$\begin{matrix} {{Vout} = {{\left( {1 + \frac{R\; 2}{R\; 1}} \right)\frac{R\; 4}{{R\; 3} + {R\; 4}}{Vip}} - {\frac{R\; 2}{R\; 1}{Vin}}}} & (1) \end{matrix}$

where Vin is the voltage at the inverting input 22 and Vip is the voltage at the non-inverting input 24. Further, if R2/R1=R4/R3, the gain A of the audio amplifier 100 can be expressed as:

$\begin{matrix} {A = {\frac{Vout}{{Vip} - {Vin}} = \frac{R\; 2}{R\; 1}}} & (2) \end{matrix}$

In order to provide N gain settings, the configuration illustrated in FIG. 3 requires 2*(N+1) resistors and 2N switches. In general, for a gain Ai, the resistances R1 and R2 can be expressed as

$\begin{matrix} {{{{R\; 1}_{A = {Ai}}} = {\sum\limits_{j = 1}^{14 - i}\; r_{j}}}{{{R\; 2}_{A = {Ai}}} = {\sum\limits_{j = {14 - i + 1}}^{14}\; r_{j}}}} & (3) \end{matrix}$

With this configuration, R1 and R3 decrease, and R2 and R4 increase, by the same amount, corresponding to the gain step size. Because gain is determined by the resistance ratio, the gain error depends on the achievable degree of matching of ratio the ratios R2/R1 and R4/R3. Because the resistances of R1 to R4 vary as the gain is switched, the constellation of R1 and R2 changes, even though the resistors r₁ . . . r₁₄ and s₁ . . . s₁₃ all have fixed positions. For the layout of R1, R2, R3 and R4, however, interleaving must be maintained for best matching at each gain setting, as will now be described. Only the layout for R1 and R2 will be described, as the layout for R3 and R4 can follow the same principles.

The layout of resistors r₁ . . . r₁₄ and their interconnection is illustrated in FIG. 4. From left to right, the order of placement of the resistors is r₇, r₉, r₅, r₁₁, r₃, r₁₃, r₁, r₁₄, r₂, r₁₂, r₄, r₁₀, r₆, and r₈. All resistors are connected, as indicated in FIG. 3, in series, thus forming a resistor chain. The switches a1 . . . a13 to which each resistor r₁ . . . r₁₄ is coupled are indicated at the top and bottom of each resistor, the taps of the resistor chain being distributed roughly half at top and half at bottom of the arrangement of resistors. With this placement, for every gain setting the resistors forming R1 and R2 are interleaved optimally. This is demonstrated by the table of FIG. 5 where the resistors r₁ . . . r₁₄ are represented by columns, each gain setting is represented by a row A1 . . . A13, and for each gain setting the shaded circles indicate the resistors corresponding to R2 and the non-shaded circles indicate the resistors corresponding to R1. It can readily be seen that for each gain setting, a high degree of interleaving has been obtained between the resistors of R1 and the resistors of R2. Resistors R3 and R4 can be implemented in a corresponding fashion.

FIG. 6 shows a layout of the components R1, R2, R3, R4, the switch bank 30 and the decoder 40 in 65 nm CMOS. In this design each resistor r₁ . . . r₁₄ is implemented with a four-line array of unit resistors of polysilicon type, and about half dummy resistors have been added to occupy otherwise vacant space in the layout and to ensure the end resistors r₇ and r₈ have neighbors on both sides for best matching. The switch bank 30 and the decoder 40 have been placed between the resistor arrays to provide an equal distance to the resistor arrays.

A single input amplifier, having a non-balanced input, may be formed simply by grounding the non-inverting input 14 of the amplifier illustrated in FIG. 2, thereby avoiding the requirement for the combination R3, R4.

The interleaving arrangement can be extended to any number of gain settings and generalized. A generalized embodiment will be described with reference to FIG. 7 in which the boxes each represent a resistive element, the numbers above the boxes represent the order of the element in the series forming the chain, and the numbers below the boxes represent the positions of the elements in the layout. The arrangement will be described in two stages, considering first the positions of the elements indicated by solid lines in diagram a) of FIG. 7, and secondly the positions of the elements indicated by solid lines diagram b) in FIG. 7.

Let N be the total number of resistor elements connected in series, in order from r₁ to r_(N). If N is even, we first divide the elements into two subsets. The first N/2 elements form one subset and the rest form the other. All N elements will be placed in a row of size N. The positions for the elements are numbered from 1 to N, from left to right. Starting with the first subset of elements which are indicated by the solid lines in diagram a), first we position element r₁ at position N/2, then the elements r₂ and r₃ at positions respectively second right and second left, to element 1, i.e., at positions N/2+2 and N/2−2, respectively. Then elements r₄, r₅, r₆, . . . r_(N/2) are positioned one after another at every alternate position on alternating sides of element r₁ in the same fashion. The arrow lines above and below the elements in diagram a) of FIG. 7 indicate the coupling between successive elements in the chain, and are illustrated progressing in a clock wise direction. Next, we deal with the second subset of elements which are indicated by the solid lines in diagram b), and first place element r_(N) at position N/2+1, then element r_(N−1), r_(N−2), . . . r_(N/2+1), at every alternate position to the last element placed. This time the coupling between successive elements in the chain progresses anti-clockwise. If N/2 is odd, the most left element will be r_(N/2), and if N/2 is even, element r_(N/2) will be at the far right.

If N is odd, we can first disregard element r_((N+1)/2) and position the even number of elements N−1 as described above, and finally, place element (N+1)/2 at either the left-most or right-most position.

Although the placement of the first subset of elements has been described with successive elements in the chain progressing alternately right then left of the initial element in the chain, the order may instead be alternately left and right of the initial element. In this case the elements of the second subset will progress alternately right and left, because the first element of the second subset is always on the opposite side to the last element of the first subset.

Although the placement of the elements has been described with the coupling between the elements progressing clockwise for the first subset of elements and then anti-clockwise for the second subset of elements, the direction of the coupling, and the position of the coupling with respect to the elements, is immaterial to the disclosure, provided that the elements are coupled in a series arrangement.

Either end of the chain may be considered to be the first port, with the other end being the second port.

The position of the elements may be expressed mathematically in the following generalized forms, for N elements r₁ . . . r_(N) series coupled in numerical order, where adjacent positions are numbered consecutively. Element r_(i) has position

$\left\lfloor \frac{N + 1}{2} \right\rfloor + {\left( {- 1} \right)^{i} \cdot 2 \cdot \left\lfloor \frac{i}{2} \right\rfloor}$ ${{for}\mspace{14mu} i} = {1\mspace{14mu} {to}\mspace{14mu} \left\lfloor \frac{N}{2} \right\rfloor}$

and position

$\left\lfloor \frac{N + 1}{2} \right\rfloor + {\left( {- 1} \right)^{i} \cdot \left( {{2 \cdot \left\lfloor \frac{N - i}{2} \right\rfloor} + 1} \right)}$ ${{for}\mspace{14mu} i} = {\left\lfloor \frac{N}{2} \right\rfloor + {1\mspace{14mu} {to}\mspace{14mu} {N.}}}$

Note that in these expressions the symbol └x┘ indicates the largest integer not exceeding the value x, and is commonly referred to as the floor function. So, for example,

$\left\lfloor \frac{4}{2} \right\rfloor = 2$ and $\left\lfloor \frac{5}{2} \right\rfloor = 2.$

Applying the above formulae, the following are examples of the order in which the elements are positioned.

Three elements: r₃, r₁, r₂.

Four elements: r₃, r₁, r₄, r₂.

Five elements: r₃, r₅, r₁, r₄, r₂.

Six elements: r₃, r₅, r₁, r₆, r₂, r₄.

Seven elements: r₅, r₃, r₇, r₁, r₆, r₂, r₄.

Ten elements: r₅, r₇, r₃, r₉, r₁, r₁₀, r₂, r₈, r₄, r₆.

Eleven elements: r₇, r₅, r₉, r₃, r₁₁, r₁, r₁₀, r₂, r₈, r₄, r₆.

Although the layout of resistor elements has been described, the disclosure is equally applicable to the layout of capacitors, inductors or semiconductor components such as transistors, which may therefore be coupled in a corresponding series arrangement and laid out in a corresponding interleaved arrangement.

Although each element has been described as a single entity, each element may comprise a series or parallel arrangement of sub-elements having the same or different resistance, capacitance or inductance, thereby enabling components having any desired value to be formed from sub-elements. In this case, some dummy sub-elements may be included in the layout that do not contribute to the in-circuit resistance, capacitance or inductance, but merely serve to enable a symmetrical layout for best matching and to occupy vacant area.

From reading the present disclosure, other variations and modifications will be apparent to the skilled person. Such variations and modifications may involve equivalent and other features which are already known in the art of integrated circuit layout, and which may be used instead of, or in addition to, features already described herein.

Although the appended claims are directed to particular combinations of features, it should be understood that the scope of the disclosure of the present disclosure also includes any novel feature or any novel combination of features disclosed herein either explicitly or implicitly or any generalization thereof, whether or not it relates to the same disclosure as presently claimed in any claim and whether or not it mitigates any or all of the same technical problems as does the present disclosure.

Features that are described in the context of separate embodiments may also be provided in combination in a single embodiment. Conversely, various features which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable sub-combination.

The applicant hereby gives notice that new claims may be formulated to such features or combinations of such features during the prosecution of the present application or of any further application derived therefrom.

For the sake of completeness it is also stated that the term “comprising” does not exclude other elements or steps, the term “a” or “an” does not exclude a plurality, and reference signs in the claims shall not be construed as limiting the scope of the claims.

The various embodiments described above can be combined to provide further embodiments. All of the U.S. patents, U.S. patent application publications, U.S. patent application, foreign patents, foreign patent application and non-patent publications referred to in this specification and/or listed in the Application Data Sheet are incorporated herein by reference, in their entirety. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, application and publications to provide yet further embodiments.

These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure. 

1. A switchable integrated electronic device, comprising: at least three elements series coupled in a chain between a first port and a second port with nodes between successive elements of the chain; and a switch circuit for coupling a selectable one of the nodes to a third port; wherein, with successive elements in the chain denoted r_(i), i=1 to N, and with adjacent positions occupied by the elements numbered consecutively 1 to N, then element r_(i) occupies position $\left\lfloor \frac{N + 1}{2} \right\rfloor + {\left( {- 1} \right)^{i} \cdot 2 \cdot \left\lfloor \frac{i}{2} \right\rfloor}$ ${{for}\mspace{14mu} i} = {1\mspace{14mu} {to}\mspace{14mu} \left\lfloor \frac{N}{2} \right\rfloor}$ and position $\left\lfloor \frac{N + 1}{2} \right\rfloor + {\left( {- 1} \right)^{i} \cdot \left( {{2 \cdot \left\lfloor \frac{N - i}{2} \right\rfloor} + 1} \right)}$ ${{for}\mspace{14mu} i} = {\left\lfloor \frac{N}{2} \right\rfloor + {1\mspace{14mu} {to}\mspace{14mu} {N.}}}$
 2. The switchable integrated electronic device as claimed in claim 1, wherein each of the at least three elements comprises a resistive element.
 3. The switchable integrated electronic device as claimed in claim 1, wherein each of the at least three elements comprises a capacitive element.
 4. The switchable integrated electronic device as claimed in claim 1, wherein each of the at least three elements comprises an inductive element.
 5. The switchable integrated electronic device as claimed in claim 1, wherein each of the at least three elements comprises a semiconductor element.
 6. An electronic circuit, comprising: at least one switchable integrated electronic device, the at least one switchable integrated electronic device comprising a first switchable integrated electronic device having a first port coupled to a first circuit input and a second port coupled to a circuit output, and an amplifier having a first amplifier input coupled to a third port of the first switchable integrated electronic device and an amplifier output coupled to the circuit output, each at least one switchable integrated circuit comprising: at least three elements series coupled in a chain between a first port and a second port with nodes between successive elements of the chain; and a switch circuit for coupling a selectable one of the nodes to a third port; wherein, with successive elements in the chain denoted r_(i), i=1 to N, and with adjacent positions occupied by the elements numbered consecutively 1 to N, then element r_(i) occupies position $\left\lfloor \frac{N + 1}{2} \right\rfloor + {\left( {- 1} \right)^{i} \cdot 2 \cdot \left\lfloor \frac{i}{2} \right\rfloor}$ ${{for}\mspace{14mu} i} = {1\mspace{14mu} {to}\mspace{14mu} \left\lfloor \frac{N}{2} \right\rfloor}$ and position $\left\lfloor \frac{N + 1}{2} \right\rfloor + {\left( {- 1} \right)^{i} \cdot \left( {{2 \cdot \left\lfloor \frac{N - i}{2} \right\rfloor} + 1} \right)}$ ${{for}\mspace{14mu} i} = {\left\lfloor \frac{N}{2} \right\rfloor + {1\mspace{14mu} {to}\mspace{14mu} {N.}}}$
 7. The electronic circuit as claimed in claim 6, comprising a second switchable integrated electronic device having its first port coupled to a second circuit input, its second port coupled to ground or another point in the circuit, and its third port coupled to a second input of the amplifier, wherein the first and second amplifier inputs are respectively inverting and non-inverting.
 8. The electronic circuit as claimed in claim 7, wherein the respective at least three elements of the first and second switchable integrated electronic devices are equal in number and wherein the respective switch circuit of the first and second switchable integrated electronic devices is adapted to couple a corresponding selectable one of the nodes of the first and second switchable integrated electronic devices to the respective third port.
 9. A method of manufacturing a switchable integrated electronic device, comprising: forming at least three electronic elements series coupled in a chain between a first port and a second port and providing a node between successive elements of the chain; forming a switch circuit for coupling a selectable one of the nodes to a third port; wherein, with successive elements in the chain are denoted r_(i), i=1 to N, and with adjacent positions occupied by the elements numbered consecutively 1 to N, then element r_(i) occupies position $\left\lfloor \frac{N + 1}{2} \right\rfloor + {\left( {- 1} \right)^{i} \cdot 2 \cdot \left\lfloor \frac{i}{2} \right\rfloor}$ ${{for}\mspace{14mu} i} = {1\mspace{14mu} {to}\mspace{14mu} \left\lfloor \frac{N}{2} \right\rfloor}$ and position $\left\lfloor \frac{N + 1}{2} \right\rfloor + {\left( {- 1} \right)^{i} \cdot \left( {{2 \cdot \left\lfloor \frac{N - i}{2} \right\rfloor} + 1} \right)}$ ${{for}\mspace{14mu} i} = {\left\lfloor \frac{N}{2} \right\rfloor + {1\mspace{14mu} {to}\mspace{14mu} {N.}}}$
 10. The method as claimed in claim 9, wherein forming the at least three electronic elements comprises forming at least three resistive elements.
 11. The method as claimed in claim 9, wherein forming the at least three elements comprises forming at least three capacitive elements.
 12. The method as claimed in claim 9, wherein forming the at least three elements comprises forming at least three inductive elements.
 13. The method as claimed in claim 9, wherein forming the at least three elements comprises forming at least three semiconductor elements.
 14. A circuit, comprising: series coupled first and second electronic element circuits, each of the first and second electronic element circuits comprising a chain of series-coupled elements; first and second switch banks coupled respectively to the first and second electronic circuits, each switch bank comprising a plurality of switches for coupling a selectable node between any two successive elements in the chain of series-coupled elements in the respective electronic element circuit to a conductor; a control circuit to control each of the plurality of switches; wherein each of the plurality of elements occupy a position in the chain of series-coupled elements for best matching of performance, in which N is the total number of elements connected in series in the chain in order from r₁ to r_(N) with r denoting a respective individual element, and when N is even, element r₁ is positioned at N/2 in the chain, element r₂ and r₃ at positions respectively second right and second left to element r₁, which are positions N/2+2 and N/2-2, respectively, with elements r₄, r₅, r₆, . . . r_(N/2) positioned one after another at every alternate position on alternating sides of element r₁ in the same fashion that applies to the first N/2 elements, which form a first subset, and a second subset of elements in the N chain of elements having a first place element r_(N) at position N/2+1, and elements r_(N−1), r_(N−2), . . . r_((N−2)+1), at every alternate position to the last element placed, and in which coupling between successive elements in the first subset progresses in a clockwise direction starting at r₁ and going to r₂, r₃, . . . to r_(N/2) sequentially and coupling in the second subset of elements progressing counterclockwise starting with element r_(N) and going to element r_(N−1), then element r_(N−2) and concluding with the final element in the subset; and when N is odd, the element r_((N+1)/2) is disregarded and the elements are positioned with the even number of elements N−1 as described above and element (N+1)/2 is placed at either a left-most or right-most position in the chain.
 15. The circuit of claim 14, wherein the elements in the chain of elements each comprise the same type of element taken from among resistive elements, capacitive elements, inductive elements, and semiconductor elements.
 16. The circuit of claim 15, comprising an audio amplifier having a first input coupled to the conductor that is connected to the plurality of switches for selective coupling to the nodes between the elements in the chain of elements.
 17. A circuit, comprising: a chain of N series-coupled electronic elements having a node between successive elements in the chain, the order of elements in the chain of N elements, with i=1, arranged with adjacent positions occupied by the elements numbered consecutively from 1 to N, with element r_(i) occupying position $\left\lfloor \frac{N + 1}{2} \right\rfloor + {\left( {- 1} \right)^{i} \cdot 2 \cdot \left\lfloor \frac{i}{2} \right\rfloor}$ ${{for}\mspace{14mu} i} = {1\mspace{14mu} {to}\mspace{14mu} \left\lfloor \frac{N}{2} \right\rfloor}$ and position $\left\lfloor \frac{N + 1}{2} \right\rfloor + {\left( {- 1} \right)^{i} \cdot \left( {{2 \cdot \left\lfloor \frac{N - i}{2} \right\rfloor} + 1} \right)}$ ${{for}\mspace{14mu} i} = {\left\lfloor \frac{N}{2} \right\rfloor + {1\mspace{14mu} {to}\mspace{14mu} {N.}}}$
 18. The circuit of claim 17, comprising a plurality of switches, each switch having a first terminal coupled to a respective node of the chain of elements and a second terminal coupled to a common conductive line, each of the plurality of switches having a control terminal coupled to a control circuit that selectively couples the nodes to the common conductive line.
 19. The circuit of claim 18, wherein each of the elements comprises a single type of electronic element taken from a group comprising resistive elements, capacitive elements, inductive elements, and semiconductor elements.
 20. The circuit of claim 19, comprising an amplifier having first and second inputs, and further comprising a second chain of electronic elements, with the first chain of elements selectively coupled to the first input of the amplifier by the switches via the common conductive line and the second chain of elements selectively coupled to the second input of the amplifier by the switches via a further conductive line. 